With Bluespec, models and testbenches can be synthesized along with legacy IP to employ emulation much earlier for modeling, verification and early software development. Bluespec makes emulation much easier, more affordable, and deployable from concept to volume silicon. We refer to these capabilities as Bluespec 2.0: running models and verification at 10s of MHz:
You may have thought that Bluespec was solely about a better design alternative than RTL. And, yes, we’ve been about that. Leading chip companies have completed many successful tapeouts with Bluespec, the industry’s only general-purpose, high-level synthesis toolset for design implementation. But, our customers also wanted us to solve even bigger challenges such as validating specifications, accelerating firmware/driver development, reducing verification efforts and making architectural tradeoffs:
Bluespec 2.0 leverages Bluespec's current tools and very special, patented and proven complex concurrency technology, atomic transactions, to solve problems that existing modeling and RTL solutions cannot. Used by the world's leading semiconductor and systems companies, Bluespec's silicon-proven high-level synthesis toolsets for ASICs and FPGAs enable:
Bluespec's customers are choosing BSV for hardware design because it provides C++/Java-like levels of abstraction and clean semantics without obscuring architecture. BSV designers retain predictability and controllability over architecture, which is, in the end, the most important driver of implementation quality. This makes Bluespec the industry's only general-purpose, high-level synthesis solution that can handle any level of abstraction and any module type, including system interconnect, datapath and complex control.
Bluespec integrates seamlessly into existing verification, debug and synthesis flows, including Cadence, Synopsys, Mentor and Magma, without requiring new methodologies or tools.