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whitepaperNEW WHITEPAPER:

High-level "plug-and-play" specification, modeling and synthesis of algorithms and datapaths using Bluespec's PAClib

WHITEPAPER:

Synthesizable Test Benches

Includes Ethernet MAC test bench case study

 
 
BLUESPEC arow

blue·spec (blu'spek)  n.  1 Closes the modeling gap  2 Solves the simulation bottleneck  3 Affordable and easy-to-use FPGA-based emulation for early modeling, firmware development and verification  4 Unifies architecture, design and verification with the only general purpose high-level synthesis that keeps designers 100% in control

WEBINARS arow

On-demand detailed technical overview presentation on Bluespec, its solutions and core technology  Presented by Rishiyur S. Nikhil, PhD, CTO


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SCE-MI: Enabling Faster IP Verification with Emulation & FPGA Prototyping  Presented by Rishiyur S. Nikhil, PhD, CTO

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NEWS arow

February 9, 2010
Bluespec Delivers Plug-and-Play Library for Algorithm and Datapath Design

PAClib enables rapid, predictable specification for optimal power/timing/area/throughput

Read more >

 
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