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whitepaperWHITEPAPER:

Synthesizable Models Enable Early Emulation for Complex IP

Run complex models at MHz speeds in weeks

WHITEPAPER:

Synthesizable Test Benches for ASIC Emulation/Prototyping or FPGAs

Ethernet MAC test bench case study:
SystemVerilog VMM versus BSV

 
 
BLUESPEC arow

blue·spec (blu'spek)   1 The Synthesizable Modeling Company™  2 Eliminates the modeling-to-RTL gap  3 Makes emulation feasible pre-RTL (not to mention more affordable and easier-to-use) for high-speed modeling, early software development & verification  4 Unifies architecture, design and verification with the only general purpose high-level synthesis

RESOURCES arow

On-Demand Webinar:
Designing Synthesizable Transactors and BFMs

Featuring Bluespec CTO Rishiyur S. Nikhil

Click here to view the webinar >

On-Demand Webinar:
10-minute technical overview of Bluespec

Featuring Bluespec CTO Rishiyur S. Nikhil

Click here to view the webinar >

 

NEWS arow

June 10, 2010
Bluespec High-Level Synthesis Toolset is Selected by Fujitsu

Read more >

March 25, 2010
Bluespec High-Level Synthesis Toolset is Selected by Panasonic

Read more >

February 9, 2010
Bluespec Delivers Plug-and-Play Library for Algorithm and Datapath Design

Read more >

 
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