Bluespec is pleased to announce it will be co-hosting the Boston RISC-V Technical Symposium, an opportunity to engage with the RISC-V community that is revolutionizing processor innovation through open source collaboration. The event, occurring February 28 in Boston, is a great opportunity for attendees to explore the global phenomenon of RISC-V and the countless creative solutions it is spurring. It is one of the 50+ trailblazing RISC-V symposiums being held around the globe this year, seeking to advance a stronger education for RISC-V ISA. Bluespec will be presenting the symposium in partnership with SiFive, the company founded by the inventors of the RISC-V architecture.

The event will kick off at 8:00 am at the Boston Burlington Marriott located at 1 Burlington Mall Road in Burlington, MA . Attendance is free and lunch will be included. Interested attendees can register for the event here. The following is the complete agenda for the event.

08:00 – 08:50 – Registration

08:50 – 09:00 – Welcome and Introduction, by Swamy Irrinki, Sr. Director of Marketing, SiFive

09:00 – 09:30 – RISC-V History and State of the Union, by Rishiyur Nikhil, ISA Formal Spec Task Group Chair, RISC-V Foundation  

09:30 – 09:50 – Ecosystem Partner Presentation

09:50 – 10:10 – Ecosystem Partner Presentation

10:10 – 10:40 – Keynote: Leading Semiconductor Design Revolution, by Krste Asanovic, Chairman of RISC-V Foundation

10:40 – 11:00 – Break

11:00 – 11:20 – RISC-V Custom SoC Solution for SSD Controller, by Nagendra Shivakumar, Sr. Technical Solutions Manager, SiFive

11:20 – 11:40 – Freedom Revolution Customizable RISC-V AI SoC Platform, by Krste Asanovic, Co-Founder and Chief Architect, SiFive

11:40 – 12:00 – Research with RISC-V at MIT CSAIL: Modular Design for Performance, Security and Formal Verification, by Adam Chlipala, Associate Professor of Computer Science, MIT

12:00 – 13:00 – Lunch and Demos

13:00 – 13:20 – RISC-V Core IP for Target Vertical Markets, by Aniket Saha, Sr. Director of Product Marketing, SiFive

13:20 – 13:40 – Formal Verification: Core Designer, by Murali Vijayaraghavan, Verification Manager, SiFive

13:40 – 14:00 – SoC IP for Target Vertical Markets, by Mohit Gupta, VP SoC IP, SiFive

14:00 – 14:30 – Keynote: RISC-V Verification and Design Using Bluespec’s High-Level Tools, by Rishiyur Nikhil, CTO, Bluespec

14:30 – 14:50 – Break

14:50 – 15:10 – Ecosystem Partner Presentation

15:10 – 15:40 – Tutorial: SiFive Core Designer, by Aniket Saha, Sr. Director of Product Marketing, SiFive

15:40 – 15:50 – Video: Design Your Own CPU!!

15:50 – 16:00 – Closing Remarks, by Gerry Benson, VP of Sales, SiFive

16:00 – 17:00 – Networking/Demos