"Atomic transactions for hardware are at the core of our technology – and Bluespec is the only company delivering such a solution for hardware modeling, verification and design."
Based on over six years of commercial development and eleven years of research at MIT, Bluespec’s patented, silicon-proven technology is built on four core elements:
- Atomic Transactions
- Control-Adaptive Parameterization
- Modern, High-Level Language Facilities
- Mainstream Technologies
Simplifying Complex Concurrency with Atomic Transactions
Atomic transactions for hardware are at the core of our technology – and Bluespec is the only company delivering such a solution for hardware modeling, verification and design. And, while atomic transactions significantly raise the level of concurrency abstraction above SystemC and RTL, they are unique in giving the engineer 100% control over architecture and micro-architecture for optimal results. Thus Bluespec's toolsets deliver high-level synthesis without the compromises inherent in other solutions. Atomic transactions simplify complex concurrency, improve communication between modules, and elevate the description and synthesis of system, control and algorithmic IP.
Atomic Transactions Enable:
- Automatic synthesis of complex control logic, which is often the source of many difficult bugs with other approaches
- Highly adaptable, reusable, and reconfigurable designs, where the toolset can automatically adapt the control logic to the specific architecture of each variant
- Rapid changes so that you can add features incrementally, explore micro-architectures quickly and make changes quickly
- Modular composition where interfaces provide an abstract specification for both inter-module communication connectivity and protocol
- Bluespec’s compiler technology performs hardware synthesis to RTL where it maximizes the concurrency of atomic transactions. This enables designs to match the power, performance and area results of hand-coded RTL, but with a significantly higher level of abstraction, succinctness and flexibility.
- With Bluespec, you think architecture, but design models, testbenches and implementations much, much faster and with many fewer bugs. And everything is synthesizable!
Delivering Extreme Reuse with Control-Adaptive Parameterization
Bluespec’s powerful, control-adaptive parameterization enables flexibility and auto-generation of control logic on a scale not possible with other approaches. With Bluespec you can parameterize a design, testbench or model with:
- Different micro-architectures just based on parameter values such as different degrees of pipelining, different degrees of data-parallelism and reuse
- Different algorithms, arbitration schemes, or functions
- Different interfaces
- Data types, including structures, elements and widths
Control-adaptive parameterization allows you to easily:
- Use a single paradigm from initial models to implementation, ensuring that the testbench used by the architect is also fully reusable by the implementer.
- Write a single source code that elaborates to different architectures based on parameter values. For example, you can build a single sorting queue parameterized by the type of data, pipelining, and sorting algorithm.
- Reuse the same IP with different I/O interfaces (for example OCP or AXI)
- Target multiple environments with different constraints on area, speed, and power (for example, a video codec for a set-top box vs. for a portable device)
- Conditionally instantiate one of several alternative modules, based on a parameter
Historically, parameterization in hardware design has only been used in minor ways, such as specifying the size of a register, FIFO or RAM. Now, with Bluespec, parameterization can for the first time be used in a control-adaptive manner, where a different choice of parameters can result in a dramatically different micro-architecture, with automatic generation of the appropriate control structures for that micro-architecture. Bluespec’s 'atomic transactions' automate the changes in control logic that are implied by every refinement, every change, even every micro-architectural change.
Providing the Facilities of Modern, High-Level Languages
Modern software engineering practice relies on advanced systems for user-defined data types and static type-checking. These increase expressive power, raise the level of abstraction, and bring greater robustness to system design. BSV brings the same advantages to hardware system design. BSV’s type system is essentially the same as Haskell’s, which perhaps has the most powerful type system of any modern programming language in production use. Specifically, BSV’s type system includes:
- User-defined enums, structs, tagged unions and arrays (these are also available in SystemVerilog), and pattern-matching notation for simplified access to such types.
- Polymorphism, i.e., the ability to parameterize types with other types. These are analogous to “template classes” in C++.
- User-defined overloading, i.e., the ability to use a common name to refer to different actual entities (operators, functions, modules) depending on the types of the arguments and results. A common example is the use of the operator “+” to refer to various addition functions over different integer, floating point, vector and matrix types.
- First class data types, allowing the designer to write expressions and functions that compute with such entities or pass them as arguments and results. In BSV, interfaces, modules, functions, and rules are all first class data types. Since functions can also express loops and recursion, this provides Turing-complete expressive power to programmatically describe hardware structures.
- Clocks and resets, allowing the definition and use of multiple clock domains. BSV clock domain discipline also ensures that synchronizers are present at all clock domain crossings.
All these facilities in BSV can be used in synthesizable code. Further, strong static checking and optimizations ensure that there is no hardware implementation overhead or penalty for using them.
Building on Mainstream Technologies
Bluespec delivers these capabilities by wrapping atomic transactions and control-adaptive parameterization inside a modern, advanced language, Bluespec SystemVerilog. Bluespec’s tools generate Verilog RTL and SystemC models from high-level source to allow seamless integration with existing tools and methodologies.
The work of Professor Arvind, Johnson Professor of Computer Science and Engineering at the Massachusetts Institute of Technology, laid the foundations for Bluespec.
Please refer to the academic resources page to get references and links to applied and core technology work performed by the university community.