Synthesizable Test Benches

You no longer develop complex test benches with RTL. Why should you have to when you target emulation and FPGA prototyping?

High-level verification languages and environments such as SystemVerilog and e/Specman, as used in VMM or OVM, may be the state-of-the-art for writing test bench IP, but they are useless for developing models, transactors and test benches to run in FPGAs for emulation and prototyping. None of these languages are synthesizable. So engineers wishing to move verification assets onto FPGAs have been designing with RTL, the same old slow, resource-intensive and error-prone way.

With BSV, Bluespec offers the industry’s best-in-class high-level synthesis language, toolset and set of IP libraries that enable powerful parameterization, reusability, and composability for modeling, verification and implementation. Bluespec provides the only general-purpose, high-level synthesis toolset for any use model (models, test benches, production IP) and design type (datapath, control, interconnect).

Use BSV to develop high flexible traffic generators, analyzers, monitors and much more that can run in emulation and prototyping. 

Learn more about Bluespec’s product for Synthesizable Test Benches: