Synthesizable Models

High-level modeling is essential for success during the hardware development of complex IP blocks. Specifications should be accurately modeled and thoroughly evaluated before implementation.

C/C++/SystemC have been the default modeling languages. But they are weak at modeling hardware concurrency and they are not generally synthesizable. Consequently, they take too much time to develop, fall short on accuracy, and cannot run in emulators to fix simulation bottlenecks.

Bluespec provides the only solution that closes the gap between models and RTL implementations. Bluespec synthesizable models interoperate with RTL, can be incrementally and selectively refined to a full implementation, and allow high-speed emulation at all stages of complex IP development.

BSV Language & Compiler

Bluespec Solutions for Hardware Models

Benefits of Synthesizable Models for Complex IP Blocks

  • High-speed model validation: Synthesizable models enable specs to be quickly and accurately modeled and emulated using real application stimulus for thorough spec validation before design RTL is started.
  • High-speed design validation: Synthesizable transactors and test benches enable easy validation of completed RTL designs against long application runs. Days of simulation time reduce to minutes.
  • System-level validation: Complex IP blocks are typically integrated into large systems. Synthesizable test benches can be scaled to full SoC test benches for integration testing and system validation.
  • Architectural exploration: Real architectural exploration requires the fast and accurate coding of architectures and the high speed validation of architectures. Bluespec’s synthesizable models enable both.
  • Refinement to implementation: Bluespec synthesizable models can be incrementally refined to production quality RTL with no area, performance, or power penalty.

Architectural Models

Can you get the model for the specification of a complex IP block running at 50 MHz in emulation in 6 weeks? High-level modeling is essential for success during the hardware development of complex IP blocks. Specifications should be accurately modeled and thoroughly evaluated before implementation. C/C++/SystemC have been the default modeling languages. But they are weak at modeling hardware concurrency and they are not generally synthesizable. Consequently, they take too much time to develop, fall short on accuracy, and cannot run in emulators to fix simulation bottlenecks.

Bluespec provides the only solution that closes the gap between models and RTL implementations. Bluespec synthesizable models interoperate with RTL, can be rapidly explored for the optimal architecture, can be incrementally and selectively refined to a full implementation, and allow high-speed emulation at all stages of complex IP development.

Synthesizable Transactors

Synthesizable transactors are challenging to develop, which diverts development focus from core project activities and puts schedule at risk. Bluespec has a library of common transactors that can be used right off-the-shelf – and, if you need something different, Bluespec has the industry’s best solution for developing your own.

While C-based transactors are not synthesizable, BSV’s unique features are making it a popular choice for many companies building synthesizable transactors, which are central to emulation/FPGA-based verification flows:

  • Atomic transactional rules and interfaces are excellent for expressing complex, fine-grain, heterogeneous parallelism, which is typical in control-dominated components (transactors, protocol engines, processors, caches, interconnects, DMAs, …)
  • Very powerful FSM sub-language
  • Excellent support for Multiple Clock Domains
  • No subsetting for synthesis—all high-level features available in synthesizable code, even high-level models

Synthesizable System Models

In order to fully exercise a design, you may need to flesh out your verification environment with system models, such as disk drives or USB devices. Or you may want to develop a golden reference model – or use a model in advance of RTL being ready for a block. If you are targeting emulation or FPGA prototyping, why get stuck with RTL or, worse yet, doing without? Bluespec synthesizable modeling lets you quickly develop these types of models – from functional to cycle-accurate – at a high-level for any type of system-level device, including complex control, interconnects and algorithms. All of these are 100% synthesizable into emulation or FPGA prototyping.

ARM AMBA-based IP Modeling Environments

With the Bluespec ARM Synthesizable Virtual Platform, you can develop synthesizable models of your ARM IP and run them in an ARM SOC model, including Linux at MHz speeds. Explore and validate architectures early. Develop firmware that works with your ARM IP model. And, easily and quickly refine your ARM IP model into a high-quality implementation.

BSV Language & Compiler

Synthesizable Test Benches

High-level verification languages and environments such as e/Specman, Vera and now SystemVerilog, as used in VMM or OVM, may be the state-of-the-art for writing test bench IP, but they are useless for developing models, transactors and test benches to run in FPGAs for emulation and prototyping. None of these languages are synthesizable. So engineers wishing to move verification assets onto FPGAs have been designing with RTL, the same old slow, resource-intensive and error-prone way.

With the powerful, 100% synthesizable capabilities of BSV, designers can leverage a modern high-level language for synthesizable verification IP. Engineers can design test benches, models and transactors at a high level of abstraction and with extreme reuse, but they can also synthesize them onto FPGAs – and they can do this as easily as they do today in simulation-only verification environments. Imagine running your test benches, models and transactors at tens of MHz.

Learn more about Bluespec’s products for Synthesizable Models: