 "With less than a week of training, we were able to significantly accelerate design and with much fewer bugs. I completed the design much faster than we did with the original Verilog RTL design. It fully passed our comprehensive regression suite, met timng, and had 30% fewer gates than the original. "Providing the engineer full control of architecture through to synthesized RTL, Bluespec enables rapid exploration of different architectures to quickly obtain an optimal, functionally correct implementation. "Bluespec is the future of design." Senthil Krishnamoorthy, Principal Engineer, Aarohi Communications, Inc. |
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Resources Welcome to the Bluespec resource center. Please bookmark this page and come back often to access our latest updates. Additional content — including archived webinars and documents & reports — will appear here regularly. White Papers/Product Briefs 2-Page Overview: Synthesizable Models Enable Early Emulation for Complex IP White Paper: Delivering Synthesizable Verification IP for Test Benches White Paper: White Paper: High-level "plug and play" specification, modeling and
synthesis of algorithms using Bluespec's PAClib 2-Page Overview: Bluespec vs. C/C++/SystemC for Modeling, Model Refinement & Design Implementation White Paper: Emulation: Enabling it on Every Desktop Videos/Webinars Designing Synthesizable Transactors and BFMs
(one hour) 10-minute technical overview of Bluespec On-demand detailed technical overview presentation on Bluespec, its solutions and core technology (one hour) SCE-MI: Enabling Faster IP Verification with Emulation & FPGA Prototyping Featuring Bluespec CTO Rishiyur S. Nikhil
Training, Support, and Others Bluespec Wiki Bluespec Discussion Forums University and Industry Courses and Research Papers and Articles |
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