 "With less than a week of training, we were able to significantly accelerate design and with much fewer bugs. I completed the design much faster than we did with the original Verilog RTL design. It fully passed our comprehensive regression suite, met timng, and had 30% fewer gates than the original. "Providing the engineer full control of architecture through to synthesized RTL, Bluespec enables rapid exploration of different architectures to quickly obtain an optimal, functionally correct implementation. "Bluespec is the future of design." Senthil Krishnamoorthy, Principal Engineer, Aarohi Communications, Inc. |
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Emulation Infrastructure Bluespec provides a truly unique set of capabilities for emulation. Together, they address affordability, setup, ease-of-use, and bottlenecks in the link and simulator – key issues to overcome for broader adoption. Designed to work with many different FPGA platforms, Bluespec’s HW/SW co-emulation stack based on the SCE-MI standard that provides fast bringup and portability, and facilitates rapid test bench re-partitioning. It supports:
And, it offers seamless integration with Bluespec transactors and synthesizable test benches on the emulation platform Of course, Bluespec also provides a general-purpose high-level synthesis language, toolset and IP libraries that enable powerful parameterization, reusability, and composability of models, test bench components, transactors and implementations. In order to achieve acceptable performance, link and simulation bottlenecks must be overcome. This inevitably means moving testbench components into the emulation platform – which can only be done quickly and effectively with general purpose, high-level design and synthesis. |
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