The Bluespec Compiler (BSC) compiles a high-level model, transactor, testbench or implementation into Verilog RTL or SystemC.

Own Your Architecture™

Bluespec is much different from a behavioral synthesis solution, which starts with software and tries to implement a hardware architecture for it. Instead, Bluespec is a very high-level hardware design solution that keeps the designer 100% in control of the architecture and micro-architecture – you own the architecture so that you have optimal control over area, power, performance and latency. Bluespec synthesizes architectures to RTL or SystemC.

Key Features

• Atomic transactions, the single most powerful tool for managing complex concurrency, for interfaces and shared resource arbitration
  
  
• Control-adaptive parameterization, which allows powerful parameterization on almost any dimension, including features and micro-architectures. Control logic is automatically and correctly generated for different compile-time parameter choices – including for different micro-architectures
  
  
• Automated formal interface contracts encapsulate protocol and connectivity into a high-level interface for correct connectivity and protocol plus implicit flow control
  
  
• Comprehensive static verification of designs to eliminate problems before simulation
  
  
• StmtFSM sub-language for the high-level specification of parallel, nested FSMs, turbocharged by atomic transactions (automated shared resource management and arbitration, implicit flow control, automated formal interface contracts, etc.)

• Fast, hierarchichal, unlimited-capacity synthesis
  
  
• BSV language uses SystemVerilog syntax plus Bluespec atomic transactions
  
  
• Synthesizable Verilog RTL or SystemC executable output

Key Benefits

• Rapid changes for architectural exploration, feature changes, bug fixes, design-by-refinement, etc.
  
  
• Designer control over architecture enables better quality of results (area, power, timing, latency, performance, …) with no compromise RTL – and much faster exploration and debug
  
  
• Orders-of-magnitude fewer bugs. One customer benchmarked a design at 1/6th the number of bugs of an equivalent RTL implementation.
  
  
• 2X to 10X productivity gains with absolutely no compromise in quality of results
  
  
• Extreme reuse through powerful parameterization, interface specifications, and much safer changes
  
  
• Ability to attack problems previously too complex for hardware description languages
  
  
• Succinct, easy-to-understand code for executable specifications, better design reviews, and higher quality

A Sampling of Applications

A large microprocessor company uses Bluespec to quickly model new architectures for next generation processors and synthesize the models to evaluate the performance in FPGA emulation

A large computer company uses Bluespec for exploration of processor architectures and successfully booted Linux on an FPGA-based processor model within 11 months of the project start

A large wireless semiconductor company uses Bluespec to accelerate verification and performance validation using synthesizable testbenches running on emulation systems

A large handset company uses Bluespec to optimize modem micro-architectures and accelerate verification using synthesizable testbenches

A large semiconductor company uses Bluespec to develop highly configurable IP blocks for their wireless platforms

A prominent IP company uses Bluespec for executable specifications and C models delivered to customers in advance of synthesizable RTL

A systems company specializing in hybrid computer systems for special purpose applications uses Bluespec to parameterize building blocks for quick configuration and composition of high-performance FPGA blocks