 "With less than a week of training, we were able to significantly accelerate design and with much fewer bugs. I completed the design much faster than we did with the original Verilog RTL design. It fully passed our comprehensive regression suite, met timng, and had 30% fewer gates than the original. "Providing the engineer full control of architecture through to synthesized RTL, Bluespec enables rapid exploration of different architectures to quickly obtain an optimal, functionally correct implementation. "Bluespec is the future of design." Senthil Krishnamoorthy, Principal Engineer, Aarohi Communications, Inc. |
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Upcoming Conferences July 13, 2010 - Bluespec User Group Meeting 2010 in Japan Click here to learn more on their website.
Upcoming and Pre-Recorded Webinars 10-minute technical overview of Bluespec Detailed technical overview presentation on Bluespec, its solutions and core technology (one hour) SCE-MI: Enabling Faster IP Verification with Emulation & FPGA Prototyping Featuring Bluespec CTO Rishiyur S. Nikhil
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