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BSV Technical White Papers

 
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kczeck



Joined: 30 Apr 2007
Posts: 68

PostPosted: Mon Apr 30, 2007 11:21 am    Post subject: BSV Technical White Papers Reply with quote

Provided here are technical white papers of interest to the BSV community.
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kczeck



Joined: 30 Apr 2007
Posts: 68

PostPosted: Mon Apr 30, 2007 11:22 am    Post subject: Achieving Timing Closure with BSV Reply with quote

This paper describes techniques used by the BSV designer to achieve timing closure.


TimingClosure.pdf
 Description:
Paper describing BSV timing closure techniques.

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 Filename:  TimingClosure.pdf
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kczeck



Joined: 30 Apr 2007
Posts: 68

PostPosted: Mon Apr 30, 2007 11:26 am    Post subject: Reliable Design with Multiple Clock Domains Reply with quote

This paper presents a series of guiding principles for the management of multiple clock domains in BSV design.


Memocode06.pdf
 Description:
Multiple Clock Domains

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crimsoncardinal



Joined: 25 Apr 2007
Posts: 66

PostPosted: Thu Nov 01, 2007 12:57 pm    Post subject: Test Results: Comparing RTL Tool Output to Hand-Designed RTL Reply with quote

Interra Systems, Inc.

Bluespec Testing Results: Comparing RTL Tool Output to Hand-Designed RTL

This document discusses Interra Systems experience with Bluespec tools and the results of its tests comparing the quality of Bluespec’s RTL results with those of hand-crafted RTL designs. It looks at area and timing results across 25 designs.



InterraReport042604.pdf
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crimsoncardinal



Joined: 25 Apr 2007
Posts: 66

PostPosted: Thu Nov 01, 2007 1:00 pm    Post subject: Bluespec for IP Delivery and Effective Debug Reply with quote

This document includes a sample design and corresponding Verilog RTL and highlights:

1. Why Bluespec SystemVerilog and its generated Verilog RTL make a terrific solution for the delivery of IP;

2. Why Bluespec's generated Verilog RTL code is straightforward to understand, debug and work with.



BSVforIPandDebug.pdf
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 Filename:  BSVforIPandDebug.pdf
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crimsoncardinal



Joined: 25 Apr 2007
Posts: 66

PostPosted: Thu Nov 01, 2007 3:42 pm    Post subject: Developing Algorithmic Designs using Bluespec Reply with quote

This paper outlines the methodology for implementing algorithmic designs using Bluespec. From the intro:

Modern SoCs often contain IP blocks or subsystems for audio, image, video, security, phone, wireless, networking and other applications. They require hardware implementation or acceleration because of low-power considerations. For many of these applications, the starting point is a software implementation, often in Matlab, C or C++, either because that is how they were originally prototyped, or because that code is the “reference” code for a public standard. In this document we outline the typical development process for implementing such algorithmic applications in Bluespec SystemVerilog (BSV).

This document is aimed at two audiences:
– Designers who just want to do such an implementation, reading this as a methodology cookbook.

– Technologists who want better to understand why BSV is advantageous for this activity. In particular, to gain insight into the apparent paradox that, while the designer specifies and controls microarchitecture precisely in BSV, it is nevertheless a very powerful “High Level Synthesis” tool.



Algorithmic_designs_in_BSV.pdf
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dan



Joined: 15 Aug 2010
Posts: 1

PostPosted: Wed Oct 27, 2010 7:54 pm    Post subject: Re: Reliable Design with Multiple Clock Domains Reply with quote

kczeck wrote:
This paper presents a series of guiding principles for the management of multiple clock domains in BSV design.


Is the code that's used in this paper available anywhere?
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