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Oyku
Joined: 27 Jul 2016
Posts: 7
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 Posted: Sun Sep 11, 2016 7:52 am Post subject: Infeasible Ramstyle in Vivado |
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I geneated some BRAMs using Bluespec Verilog.
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BRAM_DUAL_PORT#(Bit#(TExp#(N)), Bit#(64)) bN <- mkBRAMCore2Load(valueOf(TExp#(N)), False , "N.bin", False);
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I am using the generated verilog file in Vivado Design Suite with the Bluespec Library File BRAM2Load.v.Everything is working as intended without any errors. But when I checked the utilization I saw that instead of brams, Luts are used.
I added this inside the BRAM2Load.v. | Code: | | (* ram_style ="block" *) reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] |
Right now i am getting [Synth 8-3463] Infeasible ramstyle = block set for RAM RAM_reg,trying to implement using LUTRAM.
Thank you for your time. |
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quark
Site Admin
Joined: 02 Nov 2007
Posts: 495
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| Posted: Sun Sep 11, 2016 3:51 pm Post subject: Re: Infeasible Ramstyle in Vivado |
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The Bluespec release includes a directory of alternate Verilog files that you should use when synthesizing with Vivado. It is located at $BLUESPECDIR/Verilog.Vivado/ instead of $BLUESPECDIR/Verilog/. The BRAM2Load.v file there is identical to the default version but it has the attribute, which you mentioned:
| Code: | (* RAM_STYLE = "BLOCK" *)
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If you have added the attribute, I do not know why you are getting the error. Different versions of Vivado have may have different style requirements for inference or may have restrictions or bugs. What version of Vivado are you using? The provided Verilog files were written for Vivado 14.x. You may want to look on the Vivado support website to see if you're using the BRAM in a way that is restricted for BRAM inference.
I also notice that you're using a module from the BRAMCore package and not from the BRAM package (which wraps the core modules). Is there a reason that you chose to use the Core package? If you switch the using a module from the BRAM package (which is recommended), the synthesis problem might also go away. |
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Oyku
Joined: 27 Jul 2016
Posts: 7
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| Posted: Mon Sep 12, 2016 2:52 pm Post subject: |
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I tried using my code in Vivado 2016.2, 2015.4 and also after you mentioned 2014.x I tried 2014.1. Same result in all of them.
So I changed the code from BRAMCore to
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BRAM_Configure cfg = defaultValue;
cfg.allowWriteResponseBypass = False;
cfg.loadFormat = tagged Hex "0.bin" ;
BRAM2Port#(Bit#((TExp#(N))), Bit#(64)) d <- mkBRAM2Server(cfg);
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It still gave the same problem.
I commented out nearly everything other than the code above to check if something else was interfering but it still didnt work.
So I tried the single port version.
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BRAM_Configure cfg = defaultValue;
cfg.allowWriteResponseBypass = False;
cfg.loadFormat = tagged Hex "0.bin" ;
BRAM1Port#(Bit#((TExp#(N))), Bit#(64)) d <- mkBRAM1Server(cfg);
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And it is working correctly in version 2014.1, not using the lut but the block ram tiles. So there seems to be something with the BRAM2Load I believe. It is still giving the error in 2016.2. |
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Oyku
Joined: 27 Jul 2016
Posts: 7
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| Posted: Tue Sep 13, 2016 6:09 pm Post subject: |
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Ok, I solved the problem. It is working as wanted for the 2014.1 version.
I just added some (*dont_touch = "true" ) 's to all of the output registers of all of the brams and it seems it is working.  |
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