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Behavior of Wire/RWire/DWire as observed by Tcl "sim ge

 
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jeffc83



Joined: 05 Mar 2012
Posts: 5

PostPosted: Mon Mar 31, 2014 1:11 pm    Post subject: Behavior of Wire/RWire/DWire as observed by Tcl "sim ge Reply with quote

Hey, I'm trying to understand how to poke around in my design using Tcl. Specifically, I want to look at signal values as they pass through a pipelined module using Bluesim. I'm having a hard time understanding what I see when using "sim get" to inspect the signal values. The ultimate goal is to communicate interactively to/from some C++ test functions that I have, with some flexibility due to the scripting interface. Maybe there's a better way to do this (eg use BDPI, though that's more intrusive to my code and removes the flexibility). I constructed a really simple testbench to try and understand the behavior (code below). It has a counter and a rule which fires every other cycle to write the counter into a variety of destinations: Wire, RWire, DWire holding a Maybe, DReg holding a Maybe, and Reg. On every cycle, the BSV code prints out the values. The Tcl script loads the design and loops a few times printing the values it reads for comparison.

Code:
package Signals_Test;
import DReg::*;
import FShow::*;

module mkTB_Signals();
   Reg#(UInt#(16)) ctr <- mkReg(0);

   Reg#(UInt#(16)) my_reg <- mkReg(0);
   Reg#(Maybe#(UInt#(16))) my_dreg <- mkDReg(tagged Invalid);
   RWire#(UInt#(16)) my_rwire <- mkRWire;
   Wire#(UInt#(16)) my_wire <- mkWire;
   Wire#(Maybe#(UInt#(16))) my_dwire <- mkDWire(tagged Invalid);

   rule count;
      ctr <= ctr+1;
   endrule

   rule writes if (ctr%2 == 0);
      my_rwire.wset(ctr);
      my_wire <= ctr;
      my_dwire <= tagged Valid ctr;
      my_dreg <= tagged Valid ctr;
      my_reg <= ctr;
   endrule

   (* execution_order = "displayregs,displayWire,display" *)

   rule display;
      $display($time," RWire: ",fshow(my_rwire.wget));
      $display($time," DWire: ",fshow(my_dwire));
      $display;
   endrule

   rule displayregs;
      $display($time," Reg:   ",fshow(my_reg));
      $display($time," DReg:  ",fshow(my_dreg));
   endrule

   rule displayWire;
      $display($time," Wire:  ",fshow(my_wire));
   endrule
endmodule

endpackage



Then I run bluetcl with this script to watch what happens:
Code:

package require Bluesim
namespace import Bluetcl::*

flags set -sim
sim load mkTB_Signals.so

set rw [sim lookup *my_rwire*]
set dw [sim lookup *my_dwire*]
set reg [sim lookup *my_reg*]

set dreg [sim lookup my_dreg]
#set dregvalid [sim lookup my_dreg.isValid]
#set dregvalue [sim lookup my_dreg.value]

set dreg1 [sim lookup my_dreg_1]
set dreg1valid [sim lookup my_dreg_1.isValid]
set dreg1value [sim lookup my_dreg_1.value]


set w [sim lookup my_wire]
set wvalid [sim lookup my_wire.isValid]
set wvalue [sim lookup my_wire.value]

sim step 1

for { set i 0 } { $i < 4 } { incr i } {
   puts "TCL sees these values at time [sim time]"
   puts "  my_rwire: [sim get $rw]"
   puts "  my_dwire: [sim get $dw]"
   puts "  my_dreg   : [sim get $dreg]"
   puts ""


   puts "  my_dreg_1 : [sim get $dreg1]"
   puts "  my_dreg_1.isValid : [sim get $dreg1valid]"
   puts "  my_dreg_1.value   : [sim get $dreg1value]"
   puts ""

   puts "  my_reg  : [sim get $reg]"
   puts "  my_wire : [sim get $w]"
   puts "  my_wire.isValid: [sim get $wvalid]"
   puts "  my_wire.value: [sim get $wvalue]"

   puts ""
   puts ""
   sim step 1
}



Observations that puzzle me:

(1) sim get [sim lookup my_wire.isValid] always gives zero
(2) sim get [sim lookup my_rwire.isValid] always gives zero
(3) sim get [sim lookup my_rwire] is 16 bits so not sure where the Maybe valid bit goes
(4) sim get [sim lookup my_dwire] is 17 bits but the most significant (valid) bit is always set even in cycles when the dwire should default to tagged Invalid

DRegs come closest to what I want, in that I can see the state transitions and the valid bit behaves as I'd expect. So the options I come up with are:

(1) Instantiate extra DRegs and probe those
(2) Modify code to write out using BDPI instead (loses the scripting flexibility)

Am I missing something?

Is there a document that would help me out with this?

Thanks

Jeff
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