Musings on Synthesizable Modeling
On January 27th, CYBERNET SYSTEMS hosted their Bluespec User Group Meeting. In addition to presentations by Bluespec and CYBERNET, customer and industry presentations were made by Hitachi, TOPS Systems and Vennsa. The following are some pictures from the event:
CYBERNET SYSTEMS will be hosting a Bluespec User Group Meeting in Tokyo, Japan on January 27th, 2012. Details can be found on the Bluespec User Group Meeting website. In addition to presentations from users and Cybernet, Bluespec VP of Marketing, George Harper, will be presenting How BSV Enables Early Modeling, Verification & Emulation.
EETimes editor Brian Fuller has been traveling the country in a Chevy Volt seeking out stories about innovation. Along with his brother Kirk, who is the trip videographer, Brian stopped by Bluespec headquarters Friday October 7th. After a tour of the facility, Brian had a nice conversation about Bluespec with CEO Charlie Hauck, CTO Rishiyur S. Nikhil, VP Marketing George Harper, and VP Sales Gerry Desmond.
Afterward, Brian took the team out to the Chevy Volt for test drives. You can check out the video of the Chevy Volt below:
George Harper was invited to blog about his industry perspectives for EETimes’ EDA Designline. His first blog, Planned Human Obsolescence, has been posted.
Rishiyur S. Nikhil, Bluespec CTO, has a terrific article in ACM Queue this month entitled Abstraction in Hardware System Design. The article reviews how lessons about software languages may apply to hardware languages — and, it covers why software languages are not a good fit for hardware. Bluespec has long maintained that there are deep technical reasons why high-level synthesis (HLS) based on SystemC/C/C++ is not a good approach to complex, general-purpose hardware IP and SoC design and this article provides some of the foundation for that view. This is a great article for those that have experienced the limitations of SystemC/C/C++ HLS — or, for those wrestling with the complexities of todays complex IP and SoC designs and are looking for an extremely effective alternative to our decades old RTL technology, whether that’s Verilog, VHDL, SystemVerilog or, for synthesis from control-oriented or adaptive algorithmic designs, SystemC.
Here’s an excerpt from the introduction to Abstraction in Hardware System Design:
The history of software engineering is one of continuing development of abstraction mechanisms designed to tackle ever-increasing complexity. Hardware design, however, is not as current. For example, the two most commonly used HDLs (hardware description languages)—Verilog and VHDL12,9—date back to the 1980s. Updates to the standards lag behind modern programming languages in structural abstractions such as types, encapsulation, and parameterization. Their behavioral semantics lag even further. They are specified in terms of event-driven simulators running on uniprocessor von Neumann machines (and this is true even for their recent descendents, SystemVerilog and SystemC 10,11).
To read more, go to ACM Queue’s Vol. 9 No. 8 – August 2011 edition and read Abstraction in Hardware System Design by Rishiyur S. Nikhil.
Mentor recently decided to spin Catapult C into Calypto Design Systems, Inc.
Our viewpoint on what the Catapult C news says about C-based high-level synthesis was published in Deepchip. Both Mentor’s move and our viewpoint prompted an interesting follow up response from Andrew Stevens, formerly of ChipVision.
What do you get when you cross a bunch of bright engineering students that have only rudimentary hardware design experience at best, have never worked with FPGAs and have never seen BSV before, with only 6 weeks for a hardware project at the end of a four month crash course? You get some pretty amazing projects:
All of these were done in only 6 weeks, from project proposal to a complete implementation and test bench running in a Xilinx FPGA. Read about how MIT is changing the way digital design is taught — and what’s possible in very short timeframes on a first project with BSV — in the latest issue of Xilinx’s Xcell Journal, number 76, in the article: MIT Prof Uses ESL Tools, FPGAs to Teach System Architecture by Clive (Max) Maxfield. (Or, you can download a copy of the article here)
Mentor has a white paper, entitled Why You Should Optimize Power at the ESL Level, that highlights the huge advantage of attacking power through architecture exploration. We couldn’t agree more – and in fact, we co-authored a similar piece back in late 2006 with Holly Stump of Sequence (at that time) entitled ESL Synthesis + Power Analysis = Optimal Micro-Architecture.
If you read our paper, and then look at either Mentor’s White Paper or an article they authored on Electronics Weekly, you might notice that all three pieces use the same table, a summary of power results from the architectural exploration of an 802.11a WiFi transmitter:
This table came from a terrific IEEE MEMOCODE 2006 paper entitled, 802.11a Transmitter: A Case Study in Microarchitectural Exploration authored by Nirav Dave, Michael Pellauer, Steve Gerding, & Arvind. What Mentor fails to mention is that the exploration of the 802.11a transmitter, which rapidly explored 7 different micro architectures and achieved excellent Quality of Results in the process, was performed using Bluespec. In fact, that was one of the key points of the paper. One of the team members, upon learning about the use of their table remarked:
“Do they not realize the point of that paper was that it (was) written in Bluespec?”
Achieving the lowest power is not only about rapid architectural exploration, but also about:
With some tools, you might sometimes get the first. With Bluespec, with its 100% architectural transparency and 100% designer control over architecture, you get all three, consistently, without surprises.
This was the 5th year that the MEMOCODE conference, the ACM/IEEE International Conference on Formal Methods and Models for Codesign, ran a design contest. The design contest typically takes place in March, lasting for only four-to-five weeks, and anyone from the commercial or academic space can participate. On the first day of the contest, the contest organizers publish a design problem. The goal is to improve the performance of a reference implementation — and participants can use any design tools, hardware and/or software to improve the design’s performance.
2010 was the only year a BSV-based design was not entered — and the only year a BSV-based design has not won. 2007-2009 were won by MIT teams using BSV. This year, the Unlimited Class (Absolute Performance) was won by Michael Papamichael of CMU using BSV and a Xilinx ML605 FPGA board.
Michael Papamichael wrote a very nice paper outlining the design challenge, his methodology and results. Some highlights:
While reading Michael’s paper, please keep in mind that he did all that in only five weeks. We’d like to congratulate Michael for his impressive showing.
Bluespec is pleased to announce the 2011.06.D release of its Bluespec SystemVerilog products, including BSC, Bluesim, the Bluespec Development Workstation and emVM.
What’s new in this release?
The new release includes the following highlights:
For a detailed overview of what is new and included in this release, please review the release notes, which accompany the release.
How do you access this release?
Bluespec software releases, which include all tools and documentation, are available on Bluespec’s support forums for registered forum users at:
http://www.bluespec.com/forum/viewtopic.php?t=273
If you have already registered and been activated (a manual step we have to take to eliminate spammers), you will be able to see the file for download once you have logged in. If you have not yet registered, please go to the forum registration area and register:
http://bluespec.com/forum/profile.php?mode=register&sid=760a83ee02758a7c32fc440ffca3da7f
Once we have activated you for forum downloads AND you’re logged in, you will be able to see the file(s) for download.