ARM, MIPS, x86, PowerPC, SPARC, Alpha & Itanium microprocessor models, most booting real OSes

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Recently, Twitter user @avsm tweeted about a BSV-based MIPS model booting BSD UNIX at the University of Cambridge in the UK.  Add to that Bluespec’s own ARM Cortex ISS models that boot Linux and are included in its family of Synthesizable Virtual Platforms (SVP) for firmware development.  Think Virtual Platform, but running in FPGAs blazingly fast, so they can integrate with RTL IP and still run at MHz speeds — speed + accuracy.

Then add in a whole bunch more, including x86, PowerPC, SPARC, Alpha and Itanium models.  These models run the gamut from architectural pipelined to ISSes.  Most of them boot real OSes, and do it running really fast in FPGAs.

Given the breadth of real processor architectures booting real OSes in FPGAs, it’s clear that no other HLS solution comes close!

CONNECT: Configurable NoC Generator

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Creating highly configurable IP generators can be complex and time-consuming.  Simple parameterization is easy, such as designing for configurable bit widths.  What gets really hard is accounting for parameterization that handles behavior and structure: such as features, architectures, and even microarchitectures.  Doing this is not only complex, but it means inevitably having to leverage and integrate multiple tool environments such as Verilog, TCL and PERL.

BSV, with its control-adaptive, extreme parameterization, makes building highly parameterized IP easy — allowing you to parameterize on almost any dimension: features, modules, functions, architectures and micro-architectures.

Michael Papamichael used this power to win last year’s 2011 IEEE MEMOCODE design contest.  In five short weeks, he built two configurable NoC models that ran really fast, because they were synthesizable, on FPGAs.  His paper outlines this amazing, five-short-weeks accomplishment.

Even more impressive is what he managed to pull together in the midst of all his other work this past academic year.  Based partly on his entry from last year’s IEEE MEMOCODE design contest, Michael just launched CONNECT, a configurable, FPGA-friendly Network-on-Chip (NoC) generator.  This is a really impressive IP generator — configurable on many dimensions, including the choice of up to seven different network topologies — line, ring, double-ring, star, mesh, torus and fully-connected.  And, if one of these topologies doesn’t work, there’s an option to design your own fully customized topology.  But, don’t take our word for it – you can try it out yourself through his very cool web portal:

Bluespec User Group Meeting in Japan: Pictures

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On January 27th, CYBERNET SYSTEMS hosted their Bluespec User Group Meeting.  In addition to presentations by Bluespec and CYBERNET, customer and industry presentations were made by Hitachi, TOPS Systems and Vennsa.  The following are some pictures from the event:

EETimes/Avnet’s Drive for Innovation visits Bluespec

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EETimes editor Brian Fuller has been traveling the country in a Chevy Volt seeking out stories about innovation.  Along with his brother Kirk, who is the trip videographer, Brian stopped by Bluespec headquarters Friday October 7th.  After a tour of the facility, Brian had a nice conversation about Bluespec with CEO Charlie Hauck, CTO Rishiyur S. Nikhil, VP Marketing George Harper, and VP Sales Gerry Desmond.

Afterward, Brian took the team out to the Chevy Volt for test drives.  You can check out the video of the Chevy Volt below:

ACM Queue article: Abstraction in Hardware System Design

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Rishiyur S. Nikhil, Bluespec CTO, has a terrific article in ACM Queue this month entitled Abstraction in Hardware System Design.  The article reviews how lessons about software languages may apply to hardware languages — and, it covers why software languages are not a good fit for hardware.  Bluespec has long maintained that there are deep technical reasons why high-level synthesis (HLS) based on SystemC/C/C++ is not a good approach to complex, general-purpose hardware IP and SoC design and this article provides some of the foundation for that view.  This is a great article for those that have experienced the limitations of SystemC/C/C++ HLS — or, for those wrestling with the complexities of todays complex IP and SoC designs and are looking for an extremely effective alternative to our decades old RTL technology, whether that’s Verilog, VHDL, SystemVerilog or, for synthesis from control-oriented or adaptive algorithmic designs, SystemC.

Here’s an excerpt from the introduction to Abstraction in Hardware System Design:

The history of software engineering is one of continuing development of abstraction mechanisms designed to tackle ever-increasing complexity. Hardware design, however, is not as current. For example, the two most commonly used HDLs (hardware description languages)—Verilog and VHDL12,9—date back to the 1980s. Updates to the standards lag behind modern programming languages in structural abstractions such as types, encapsulation, and parameterization. Their behavioral semantics lag even further. They are specified in terms of event-driven simulators running on uniprocessor von Neumann machines (and this is true even for their recent descendents, SystemVerilog and SystemC 10,11).

To read more, go to ACM Queue’s Vol. 9 No. 8 – August 2011 edition and read Abstraction in Hardware System Design by Rishiyur S. Nikhil.

Xilinx Xcell Journal Article: Amazing MIT FPGA Projects & BSV

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What do you get when you cross a bunch of bright engineering students that have only rudimentary hardware design experience at best, have never worked with FPGAs and have never seen BSV before, with only 6 weeks for a hardware project at the end of a four month crash course?  You get some pretty amazing projects:

  • A Viterbi Decoder
  • The first hardware implementation of a new wireless algorithm
  • A vision algorithm for a robotic bee project at Harvard
  • Data cache movement extensions to the PowerPC
  • H.265 motion estimation

All of these were done in only 6 weeks, from project proposal to a complete implementation and test bench running in a Xilinx FPGA.  Read about how MIT is changing the way digital design is taught — and what’s possible in very short timeframes on a first project with BSV — in the latest issue of Xilinx’s Xcell Journal, number 76, in the article: MIT Prof Uses ESL Tools, FPGAs to Teach System Architecture by Clive (Max) Maxfield.  (Or, you can download a copy of the article here)

The unnamed tool behind Mentor’s optimizing power white paper

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Mentor has a white paper, entitled Why You Should Optimize Power at the ESL Level, that highlights the huge advantage of attacking power through architecture exploration.  We couldn’t agree more – and in fact, we co-authored a similar piece back in late 2006 with Holly Stump of Sequence (at that time) entitled ESL Synthesis + Power Analysis = Optimal Micro-Architecture.

If you read our paper, and then look at either Mentor’s White Paper or an article they authored on Electronics Weekly, you might notice that all three pieces use the same table, a summary of power results from the architectural exploration of an 802.11a WiFi transmitter:

This table came from a terrific IEEE MEMOCODE 2006 paper entitled,  802.11a Transmitter: A Case Study in Microarchitectural Exploration authored by Nirav Dave, Michael Pellauer, Steve Gerding, & Arvind.  What Mentor fails to mention is that the exploration of the 802.11a transmitter, which rapidly explored 7 different micro architectures and achieved excellent Quality of Results in the process, was performed using Bluespec.  In fact, that was one of the key points of the paper.  One of the team members, upon learning about the use of their table remarked:

“Do they not realize the point of that paper was that it (was) written in Bluespec?”

Achieving the lowest power is not only about rapid architectural exploration, but also about:

  • Enabling no compromises in QoR relative to the same micro-architecture in RTL
  • Reaching, in the shortest amount of time and in a predictable fashion, any micro-architecture the designer can envision

With some tools, you might sometimes get the first.  With Bluespec, with its 100% architectural transparency and 100% designer control over architecture, you get all three, consistently, without surprises.